Big Blue has officially uncloaked its nascent Power7 processor. According to William Starke of IBM, the 8-core chip is expected to feature 1.2B transistors and will be capable of achieving 20,000 coherent operations in flight.
Starke – who revealed details of the new processor at Hot Chips ’09 – also noted that the Power7 would include 12 execution units per core, 32 threads per chip along with advanced pre-fetching data and instruction sets.
“Power7 is an 8-core, high performance server chip. A solid chip is a good start. But to win the race, you need a balanced system. Power7 enables that balance,” explained Starke.
Starke noted that the Power7 offered “multiple optimization points,” such as improved energy efficiency, upgraded thread performance, dynamic allocation of resources and an “extreme” increase in socket throughput. In addition, the Power7 provides scalability up to 32 sockets, 32MB on chip eDRAM shared L3, dual DDR3 memory controllers, 100GB/s memory bandwidth per chip (sustained), 360GB/s SMP bandwidth/chip and 256KB L2 per core.
“Moving L3 onto Power7 along with advances in signaling technology enables significant raw bandwidth growth for both memory and I/O subsystems…Advanced scheduling improves Power7’s ability to utilize memory bandwidth,” added Starke.
The Power7 is reportedly designed to accommodate multiple system configurations, including 2/4s blades and racks (single chip organic), high-end and mid-range (single chip glass ceramic) and computer intensive (Quad chip MCM).
