AMD showcases Trinity at Fusion Developer Summit

AMD showcased its upcoming Trinity APU today at the first annual Fusion Developer Summit in Bellevue, Washington.

According to senior VP Rick Bergman, Trinity – slated to launch in 2012 – will be approximately 50% faster than AMD’s current A-Series APU, previously codenamed “Llano.”

“Trinity is based on our [enhanced] x86 bulldozer core. We tested the silicon a few weeks ago in our labs and confirmed a 50% performance increase,” Bergman told developers, reporters and analysts during a keynote address this morning.

“But for now, for 2011, the A-series APU [Llano] is the best in its class this year. There is nothing that even comes close.”

In addition, Bergman confirmed AMD has thus far shipped millions of Fusion APU units, with the number expected to “exceed tens of millions” by the end of 2011.

The senior VP emphasized AMD was following a strategy of delivering compelling platforms across multiple form factors – including tablets – and  said the company remained on track to achieve a whopping 10 teraflops of compute performance in a notebook by 2020.

Meanwhile, AMD Corporate Fellow Phil Rogers detailed the company’s roadmap for its Fusion System Architecture (FSA). As Rogers noted, it is absolutely essential for both the hardware and software aspects of the APU to evolve concurrently. 

“The first APUs from AMD dramatically increased processing performance while consuming less power, and now we are building upon that achievement with our next-gen [platforms],” he explained.

“Future innovations are intended to make the different processor cores more transparent to programmers. They can then seamlessly tap into the gigaflops of power-efficient performance available on the APU and design even faster, more visually stunning applications on a wide range of form factors.”

Indeed, AMD is currently focused on evolving APU architecture to make it appear as a unified processing element to the software programmer. As such, the company will be taking a number of “evolutionary steps” through 2014, including:

  • Support for C++ features that more fully leverage the GPU as a parallel processor.
  • User-mode scheduling for lower latency task dispatch between CPUs and GPUs.
  • Unified memory address space and fully coherent memory shared by the CPU and GPU so they operate seamlessly together.