MIT researchers have unveiled an ultra-high-definition, or Quad HD, chip, the first to be able to handle the new HEVC video standard in real time.
The chip, built by by the Taiwan Semiconductor Manufacturing Company, isn’t intended for commercial release. But, says MIT graduate student Mehul Tikekar, “Because now we have the chip with us, it is now possible for us to figure out ways in which different types of video data actually interact with hardware. People don’t really know, ‘What is the hardware complexity of doing, say, different types of video streams?’”
Like older coding standards, the High-Eficiency Video Coding Standard exploits the fact that in successive frames of video, most of the pixels stay the same. Transmitting only those that change saves a great deal of bandwidth.
The first step in the encoding process is thus to calculate ‘motion vectors’ — mathematical descriptions of the motion of objects in the frame.
On the receiving, end, though, these descriptions don’t yield a perfectly faithful image, as the orientation of an object and the way it’s illuminated can change as it moves. The next step, therefore, is to add a vector-based information to correct for this. Finally, the motion vectors and the corrective information are run through a standard data-compression algorithm, and the results are sent to the receiver.
The new chip performs this process in reverse. To increase efficiency – like most video chips – it ‘pipelines’ the decoding process. But the MIT researchers have included a couple of other tricks to take this even further. The application of the corrective data, for instance, is a single calculation known as matrix multiplication.
“We observed that the matrix has some patterns in it. In the new standard, a 32-by-32 matrix, representing a 32-by-32 block of pixels, is multiplied by another 32-by-32 matrix, containing corrective information. In principle, the corrective matrix could contain 1,024 different values,” says Tikekar.
But in practice, the team found there are only 32 unique numbers, so that if one’s efficiently implemented, the same hardware can be usedto do the rest.
Similarly, the team found a more efficient way to store video data in memory. The most basic way would be to store the values of each row of pixels at successive memory addresses; then, the values of pixels that are next to each other in a row would also be adjacent in memory, but the value of the pixels below them would be far away.
In video decoding, however, “it is highly likely that if you need the pixel on top, you also need the pixel right below it,” says graduate student Chiraag Juvekar. “So we optimize the data into small square blocks that are stored together. When you access something from memory, you not only get the pixels on the right and left, but you also get the pixels on the top and bottom in the same request.”
