Mentor Graphics and ARM have debuted a platform blueprint for testing RISC-based processor designs.
The reference flow provides documentation, seamless interface and scripts that accelerate the development of a complete test solution for ARM IP based on the Tessent test tools from Mentor.
As expected, the flow is optimized for high test quality, lower test cost and shortened design-for-test development schedules.
According to ARM rep Teresa McLaurin, current-gen SoCs typically contain hundreds of memory subsystems consisting of several types of individual SRAMs, including single- and dual-port SRAM, register files and ROMs.
Within each subsystem, the memories may range from high-speed SRAMs operating at higher voltages to power-optimized SRAMs running at reduced voltage. All such memories have different test and/or repair requirements, depending on the size of the individual memory instances, total SoC memory size, process defect level and maturity.
The Tessent platform offers a completely automated memory test and repair solution, including at speed testing with 100% accurate logical-to-physical mapping of ARM Artisan memories.
“In addition to the many memory SoC subsystems, some of the memories are further embedded within processor cores which have been custom tailored to achieve the highest performance and lowest power in the smallest footprint,” McLaurin explained.
“The additional complexity added by the need for proper test – and in some cases, repair of the memories contained in these optimized cores – mandates a test and repair solution that achieves the highest yield with minimal impact on SoC performance, power, footprint or cost.”
As such, ARM and Mentor have collaborated to enable Tessent support for the ARM MBIST core interface – which provides one or more interfaces for each embedded core, enabling full testing of every memory within each core with minimum impact on core power, performance or area.
Indeed, the ARM-Mentor test flow supports comprehensive testing of ARM cores and logic, as well as embedded memories used in customer SoCs. The platform also employs the Mentor scan-based design-for-test and automatic test pattern generation (ATPG) tools with embedded compression, as well as memory BIST with self-repair technologies.
In addition, the test flow defines all steps necessary for incorporating and verifying test compression and memory BIST IP, while generating all necessary test patterns. The automation flow is further simplified via default scripting and configuration files.
