Synopsys and Samsung have taped out the first test chip based on the latter company’s 14LPE process.
“[Although] the FinFET process offers significant power and performance benefits compared to the traditional planar process, the move from two-dimensional transistors to three-dimensional transistors introduces several new IP and EDA tool challenges such as modeling,” a Samsung rep explained.
“[Our] multi-year collaboration delivered the foundational modeling technologies for 3D parasitic extraction, circuit simulation and physical design-rule support of FinFET devices.”
Samsung exec Dr. Kyu-Myung Choi expressed similar sentiments, noting that while FinFET transistors were capable of delivering lower power consumption and higher device performance, they also posed “tough challenges.”
“We chose Synopsys as our FinFET collaboration partner to solve these challenges, because of our successful history together at 20 nanometer and other nodes,” said Choi.
According to Choi, the above-mentioned test chip will enable the correlation of the simulation models to the FinFET process and contains test structures, standard cells, a PLL and embedded SRAMs.
“The memory instances include high-density SRAMs designed to operate at very low voltages and high-speed SRAMs to validate the process performance,” he added.
Next-gen (ARM-powered) Samsung chips based on the above-mentioned 14LPE process are expected to boast significant power and performance improvements, which will facilitate the design of more advanced smartphones and tablets with longer-lasting battery life.
