Intel has announced plans to introduce an advanced 3D transistor design into high-volume manufacturing at the 22-nanometer (nm) node in its upcoming “Ivy Bridge” chipset.
Dubbed “Tri-Gate,” the new transistor represents a “fundamental departure” from the two-dimensional planar transistor structure powering virtually all modern electronic devices to-date.
“Intel’s scientists and engineers have once again reinvented the transistor, this time utilizing the third dimension,” Intel CEO Paul Otellini told reporters during a briefing in San Francisco.
“Amazing, world-shaping devices will be created from this capability as we advance Moore’s Law into new realms.”
According to Intel, scientists have long recognized the benefits of a 3D structure for sustaining the pace of Moore’s Law as device dimensions become so small that physical laws act as barriers to advancement.
However, what is key to today’s announcement is Intel’s ability to deploy its 3D Tri-Gate transistor design into high-volume manufacturing, which is expected to usher in the next era of Moore’s Law along with a new generation of devices.
Indeed, Intel’s 3D Tri-Gate transistors enable chips to operate at lower voltage with reduced leakage, resulting in improved performance and energy efficiency.
The new capabilities will also provide chip designers with the flexibility to choose transistors targeted for low power or high performance, depending on the application.
For example, 22nm 3D Tri-Gate transistors offer up to 37% performance increase at low voltage versus 32nm planar transistors. This means it is ideal for use in small handheld devices, which operate using less energy to “switch” back and forth. Alternatively, the new transistors consume less than half the power when at the same performance as 2-D planar transistors on 32nm chips.
So, how does the new 3D transistor differ from its predecessor on an architectural level?
Well, the traditional “flat” two-dimensional planar gate is replaced with an ultra-thin three-dimensional silicon fin that rises up vertically from the silicon substrate. Control of current is accomplished by implementing a gate on each of the three sides of the fin – two on each side and one across the top – rather than just one on top, as is the case with the 2-D planar transistor.
The additional control facilitates as much transistor current flowing as possible when the transistor is in the “on” state (for performance), and as close to zero as possible when it is in the “off” state (to minimize power), and enables the transistor to switch very quickly between the two states (again, for performance).
“Just as skyscrapers let urban planners optimize available space by building upward, [our] 3-D Tri-Gate transistor structure provides a way to manage density,” an Intel rep explained.
“Since these fins are vertical in nature, transistors can be packed closer together, a critical component to the technological and economic benefits of Moore’s Law. For future generations, designers also have the ability to continue growing the height of the fins to get even more performance and energy-efficiency gains.”
