Seoul (Korea) – Samsung says it has developed a new “3D” package, which reduces space requirements and increases performance capabilities of today’s multi-chip packages. The company plans to use the technology to improve its NAND Flash packaging starting in 2007.
Memory stacks are widely use as a solution in multi-chip packages (MCP) today as they offer semiconductor firms to bump the capacity of their chips without increasing the footprint of chips. When more and more transistors require more and more area space on a package and scaling of the production process does not provide enough real estate, the industry uses a technology called “die-stacking.”
However, current stacks typically used for Flash memory or DRAM memory chips come with a performance and size penalty, as dies are not directly connected. Today’s MCPs use wire bonding, which not only can create a bandwidth bottleneck, but also use up substantial space by creating vertical gaps between dies. There are additional running down the edge of the dies, which results in a slight increase of the footprint of a single die.
Samsung believes that its new wafer-level processed stack package (WSP) successfully tackles these shortcomings. Rather than using wire-bonding, Samsung has created micron-sized holes that penetrate through the silicon vertically to connect circuits directly. As a result, there is no need for gaps of extra space and wires protruding beyond the sides of the die. The company claims that the WSP is 30% thinner a comparable MCP; footprint space savings are claimed to be about 15%.
According to Samsung the technology will enable manufacturers of mobile and consumer electronics devices to achieve better electrical performance and design slimmer and high-performance handset designs that provide improved battery time. The technology will enter mass production in 2007, Samsung said, and will only be used for NAND Flash packages initially. However, the firm plans to use WSP for server DRAM stack packages sometime down the road. The first WSP built was a 16 Gb memory device that stacks eight 2 Gb NAND chips, the firm said.
A similar stacking approach was described by Intel at the Spring Developer Forum in March 2005, where Justin Rattner, then head of the corporate technology group and today chief technology officer, outlined the firm’s ideas of using “through silicon via” interconnection technology to create “3D” packages.