San Francisco (CA) – Integrated circuit designers will come together next month in San Francisco to get updates on hardware developments at the annual IEEE International Solid State Circuits Conference (ISSCC). Among the more visible presentations will be a next-generation Cell processor as well as AMD’s quad-core Opteron and Intel’s 80-core Teraflop processor.
The 119-page program of the conference provides a first glimpse of what we may hear at the ISSCC, which will begin on February 11. Sony, Toshiba and IBM, short STI, will present first details about a 65 nm Cell processor design, which, apparently, already runs at 6 GHz and 1.3 volts in STI’s labs.
The updated Cell will use two power supplies to increase SRAM stability as well as performance, but STI promises that actual logic power consumption will decrease. The current Cell processor, used in Sony’s Playstation 3 game console, is manufactured in a 90 nm process and runs at a clock speed of 3.2 GHz.
AMD plans to provide more details about its native quad-core Opteron processor, code-named “Barcelona.” According to the conference materials, the design of Barcelona builds on the current Opteron dual-core generation and “employs power- and thermal-management techniques throughout”. AMD is also expected to describe its DDR3 transition plans.
Intel apparently has an update to its 80-core processor that was first presented at the 2006 Fall IDF conference. The processor, which was clocked at 3.1 GHz at IDF, has reached 4 GHz, while retaining the original 20 MB of SRAM. Performance climbs from a claimed 1 TFlops at the IDF to 1.28 TFlops in this new version. Most impressive, however, is the described power consumption: According to Intel, the 80-core, 100-million-transistor-die is rated at power consumption of just 98 watts (at 1 TFlops).