The device, called a Phase-state Low Electron(hole)-number Drive Memory, or PLEDM, offers an ideal combination: lower power and faster read and write cycle times than DRAM. PLEDM is also more scalable to well beyond the levels where DRAM cells become problematic.
Hitachi says the cell will be ready for production by the time DRAM designs reach the 1-Gbit level.
In the PLEDM, each bit of data is stored in a unique stacked structure, in which a small transistor is fabricated over the gate of a larger, conventional MOS transistor.
The PLEDM cell operates by sensing the state of about 1,000 electrons trapped between unique insulating barriers in the channel region of the upper transistor. These electrons are controlled by a side gate on the transistor, and their state in turn controls the gate of the larger transistor below, providing signal gain within the memory cell.
The researchers demonstrated fabrication of the PLEDM transistor on oxide using a 0.2-micron process.
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