Mitsubishi Electronics has announced the release of the industry’s first silicon that combines DRAM and logic with a kilobit memory bus for 3D graphics.
The 3D-RAM5 offers 40MB of graphics memory, plus hardware accelerator, linked by a 1024-bit, 9GBps bus for high-performance 3D graphics rendering, company officials said.
A typical application uses at least four pieces of 3D-RAM5 per system, resulting in an unmatchable 36GBps minimum aggregate data bandwidth from the frame buffer DRAM.
The 3D-RAM5 integrated frame buffer memory architecture integrates four times the density of the previous fourth-generation 3D-RAM into a package that is only 3.2 percent larger. As result, 3D-RAM5 supports high-resolution, large-screen displays with 75 percent fewer chips for high-end 3D graphics applications.
Mitsubishi says the 3D-RAM5 is functionally and electrically backward-compatible with previous 3D-RAM generations. Samples are now available, with volume production scheduled to begin in the fourth quarter of 1999.
Additional information on the Mitsubishi Electric Semiconductor Group is available at www.mitsubishichips.com.