Magnetoresistive random access memory (MRAM) will, according to Motorola Labs, hit the market in approximately three years. Motorola has built fully functional prototypes of a 256-kilobit MRAM using 0.6-micron CMOS technology. Moreover, company representatives say 4-Mbit MRAM using a sub-0.2-micron CMOS process will come to market in 2004.
Motorola and its research partner, the Defense Advanced Research Projects Agency, are banking on the possibility that MRAM memory may overshadow both flash and ferroelectric memory in the battle for next generation non-volatile memory dominance. Besides the ability to maintain memory without power, MRAM’s architecture is particularly durable. So far, tests have shown MRAM exhibiting no signs of degradation in resistance after 10 billion read-write operations, which appears to be superior to flash and ferroelectric memory. Read and write times are very fast at a few tenths of a nanosecond.
Skeptics of the technology focus on the production challenges associated with the extremely thin tunneling barrier that separates the two magnetic layers as well as the contamination problems caused by the use of new materials in MRAM.
Read the source article at eetimes.com.